Conductive interconnections on integrated circuits typically take the form of trenches and vias in the background art. In modern deep submicron integrated circuits, the trenches and vias are typically formed by a damascene or dual damascene process. Copper is currently used in ultra large scale integration (ULSI) metallization as a replacement for aluminum due to its lower resistivity and better electromigration resistance. Electrochemical copper deposition (ECD) has been adopted as the standard damascene or dual damascene process because of larger grain size (good electromigration) and higher deposition rates. More particularly, electrochemical plating (ECP) (electroplating) is well suited for the formation of small embedded damascene feature metallization due to its ability to readily control growth of the electroplated film for bottom-up filling, and the superior electrical conductivity characteristics of the electroplated film.
However, there are problems relating to the quality of the deposited metal film. One challenge facing damascene and dual damascene processing is the formation of defects, such as pits, voids and swirling defects. A number of obstacles impair defect-free electrochemical deposition of copper onto substrates having submicron, high aspect features. Thus, improved methods, systems, and apparatus for ECP processes is desirable.